Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. PLDs include, for example, field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), mask programmable devices such as Application Specific ICs (ASICs), fuse and antifuse devices, and devices in which only a portion of the logic is programmable.
One type of PLD, the FPGA, typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes, e.g., DLLs, RAM, processors, and so forth. The interconnect structure, CLBs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 1 is a simplified illustration of an exemplary FPGA. The FPGA of FIG. 1 includes an array of configurable logic blocks (LBs 101a–101i) and programmable IOBs (I/Os 102a–102d). The LBs and I/O blocks are interconnected by a programmable interconnect structure that includes a large number of interconnect lines 103 interconnected by programmable interconnect points (PIPs 104, shown as small circles in FIG. 1). PIPs are often coupled into groups (e.g., group 105) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block.
FIG. 2 illustrates a configurable logic block (CLB) for one type of FPGA, the Virtex®-II FPGA from Xilinx, Inc. The Xilinx Virtex-II CLB is further described in pages 46–54 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these pages, but otherwise reserves all copyright rights whatsoever.)
CLB 200 of FIG. 2 includes four similar slices SLICE—0–SLICE—3. Each slice includes two lookup tables (LUTs) 201 and 202, a write strobe generator circuit 205, two carry multiplexers CM1 and CM2, two additional multiplexers MUX1 and MUX2, and two output memory elements 203 and 204.
Each LUT 201, 202 can function in any of several modes. When in lookup table mode, each LUT has four data input signals IN1–IN4 that are supplied by the FPGA interconnect structure (not shown) via input multiplexers (not shown). (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) When in RAM mode, input data is supplied by an input terminal RAM—DI—1, RAM—DI—2 to the DI terminal of the associated LUT. RAM write operations in both LUTs are controlled write strobe generator circuit 205, which supplies a write strobe signal WS to both LUTs based on RAM control signals provided by the interconnect structure.
Each LUT 201, 202 provides two output signals. A first output signal OUT1 is provided to an associated multiplexer MUX1, MUX2, which selects between the LUT output signal and an associated register direct input signal Reg—DI—1, Reg—DI—2 from the interconnect structure. Thus, each LUT can be optionally bypassed. The output of each multiplexer MUX1, MUX2 is provided to the data input terminal D of an associated output memory element (203, 204 respectively). Memory elements 203 and 204 are clocked by a clock signal CK (e.g., provided by a global clock network) and controlled by various other register control signals (e.g., from the interconnect structure or provided by configuration memory cells of the FPGA). Each memory element 203, 204 provides a registered output signal Q1, Q2. The output of each LUT 201, 202 is also provided to an output terminal D1, D2 of the CLB. Thus, each output memory element can be optionally bypassed. The Virtex-II slice also includes output multiplexers (not shown) that select from among the various output signals of the slice and provide the selected signals to the FPGA interconnect structure.
The second output signal from each LUT 201, 202 controls an associated carry multiplexer CM1, CM2. The carry multiplexers form part of a vertical carry chain that traverses the slice from a carry in terminal CIN to a carry out terminal COUT.
FIG. 3 provides a simplified illustration of a typical logic block in a PLD. The logic block includes four input multiplexers IA–ID, a 4-input lookup table (LUT), an output memory element ME, and an output multiplexer OM controlled by a configuration memory cell MO. Each of input multiplexers IA–ID optionally selects one input signal from those available in the interconnect structure. Input multiplexers IA–ID are typically controlled by configuration memory cells (not shown). Input multiplexers IA–ID provide the data input signals A–D, respectively, to the LUT, which in turn provides a LUT output signal O to output memory element ME and output multiplexer OM. Output memory element ME is clocked by clock signal CK and provides registered signal Q to output multiplexer OM. Under the control of configuration memory cell MO, output multiplexer OM provides one of signals O and Q to the logic block output terminal OUT, and hence to the PLD interconnect structure.
Power consumption is an increasingly important consideration in integrated circuits (ICs), including PLDs. The circuit shown in FIG. 3 is widely used in PLDs. Therefore, it would clearly be desirable to provide a different circuit that can perform at least the same functions while consuming less power.